Forming patterns with a tight pitch (e.g., below a 30 nanometer (nm) pitch) has become increasingly desired for fabricating advanced semiconductor devices. For instance, a 7 nm fin field effect transistor (finFET) has a fin pitch of 27 nm.
Such an aggressive fin pitch is achieved either by self-aligned quadruple pattering (SAQP) whereby a sidewall image transfer (SIT) technique is performed twice, or extreme-ultraviolet (EUV) lithography in conjunction with self-aligned double pattering (SADP). Both approaches are, however, extremely complex and costly.
Therefore, there is a need for tight pitch patterning with a reduced complexity and cost.